The present invention relates to an electroless gold plating solution, a method of plating with gold by using the same, and an electronic device plated by using the same.
As a prior electroless gold plating solution is known one containing, as major components, potassium dicyanoaurate (I), potassium cyanide, and a borane compound as disclosed in "Plating", Vol. 57 (1970), pages 914 to 920. According to the technique, a plating solution having a deposition rate of 1 .mu.m/h can be obtained. However, if the electroless gold plating solution is applied to circuit boards having surface conducting paths with the interval between the conducting paths small, gold is liable to deposit even on the insulator surface between the conducting paths. In addition, the electroless gold plating solution contains a large amount of cyanide ions, which causes safety problems in the plating operation and in the treatment of its waste solution.
As an electroless gold plating solution that contain no cyanide ions, one containing, as major components, tetrachloroaurate (III) and hydrazine is disclosed in U.S. Patent No. 3,300,328, and one containing, as major components, potassium tetrachloroaurate (III) and a borane compound is disclosed in Japanese Patent Publication No. 20353/1981. However, the electroless gold plating solutions disclosed in U.S. Pat. No. 3,300,328, and Japanese Patent Publication No. 20353/1981 have the problem that because the gold ion in the gold complex is trivalent a larger amount of a reducing agent is required in comparison with the case using potassium dicyanoaurate (I). Further, the electroless gold plating solution disclosed in U.S. Pat. No. 3,300,328 has such a problem that it is unstable to cause precipitation in the plating solution within about 2 hours, which does not allow the continuation of the plating.
Now the relationship between gold plating and electronic devices will be described. Electronic computers can be mentioned as a typical example where this relationship is most conspicuously noticed. As described in "Saiensu", Vol. 13 (1983), pages 13 to 25, in electronic computers, it is possible to decrease the delay of electric signals due to a circuit board by mounting semiconductor chips on the circuit board highly densely, and as a result the computing speed of the electronic computer can be improved. To increase the packing density of semiconductor chips, it is required to increase the density of the surface conducting paths of the circuit board. On the other hand, to join semiconductor chips by soldering, and to carry out engineering change such as wiring alteration by wire bonding, it is required that the top surface of the surface conducting paths of the circuit board is covered with metal layers made of gold. In particular, the thickness of metal film at the surface conducting paths where wire bonding will be effected has to be 0.5 .mu.m or over to guarantee the joint reliability of the wire bonding. Consequently, to improve the packing density of semiconductor chips, namely, to realize a high-speed electronic computer, it is essential to provide a method of forming a gold film having a thickness of 0.5 .mu.m or over on conducting paths that are electroplating and are highly dense and complicated in shape.
Hitherto, electroplating has been used widely to form a gold film having a thickness of 0.5 .mu.m or over on a conductor by plating. However, if the above circuit board is plated with gold, then for electrically isolated conducting paths that are present in great numbers on the circuit board, conducting paths for continuity are to be formed between the electrically isolated conducting paths and it is required that the conducting paths are cut after the plating. For that purpose, the interval between the conducting paths whereby parts actually can be mounted cannot be made smaller than 400 .mu.m. Therefore, when gold electroplating is employed, the wiring density for semiconductor chips is decreased due to the presence of the conducting paths for continuity, leading to a problem that the improvement in the packing density of semiconductor chips is limited. Further, if the above electroless plating solution containing cyanide ions is used, although the above problem involved in the electroplating can be solved, gold is also liable as described above to deposit on a part of the insulator between conducting paths where the interval between the conducting paths is small. In particular, this phenomenon takes place noticeably in the case of a circuit board having surface conducting paths whose interval is 200 .mu.m or below. Therefore, when the above electroless gold plating solution containing cyanide ions is applied for the production of a circuit board having surface conducting paths whose interval is 200 .mu.m or below, the yield becomes poor. The above electroless gold plating solutions containing no cyanide ions are also unstable, and they are impossible to be applied to the mass production of a circuit board having surface conducting paths whose interval is 200 .mu.m or below, for the similar reason to the above electroless gold plating solution containing cyanide ions.